It is now common practice in dynamic random access memories (DRAMs) to boost voltage on a word line to above V.sub.dd in order to store a full memory charge into the memory cells associated with the boosted word line during an "active restore" phase of the DRAM operation. It is often desirable in these and other integrated circuits to boost other nodes to a voltage above the V.sub.dd or voltage supply level as well.
Driving and boosting heavily loaded signal lines, however, requires a large amount of power. In a conventional boosting design, a boosting capacitor is connected between the node to be boosted and a switched voltage supply source such as an internal signal that swings from zero volts to V.sub.dd. The capacitance signal node to be boosted is at the supply voltage V.sub.dd. Then, the voltage supply is applied to one electrode of the boosting capacitor driving the other electrode of the capacitor to a voltage level boosted above V.sub.dd. Since this second electrode is connected directly to the signal node, the signal node also is boosted above the V.sub.dd level.
One disadvantage of this method is that the large boosting capacitor generally required is completely charged and discharged during every cycle of operation. Large amounts of power are consumed. Another disadvantage is that the charging of the signal node is slowed because the boosting capacitor is permanently connected thereto, thereby adding to the RC time constant.
One conventional solution to the above problem is to connect the boosting capacitor to the signal node through a transistor with a gate electrode that is boosted at an appropriate time by a second capacitor. As will be described in more detail below, this conventional solution stores a less than optimum voltage level on the boosting capacitor during the reset phase of the operation cycle. A need has therefore arisen for a node voltage-boosting circuit that will isolate the boosting capacitor from the signal node while the signal node is being charged to V.sub.dd, and will retain substantial charge in the boosting capacitor during the reset phase of the operation cycle.